/* Definitions for native events on Cray X1.
    These defines produce unique values for each event that can be counted on Cray X1.
    They are derived from values in the Cray file sys/hwperfmacros.h.
    A native event on Cray X1 consists of the chip, the register, and the event.

    The following defines encode that information into a 32-bit quantity as follows:
    0N00 0000 0000 0000 00CC 000R RRRR 00EE
    Where:
     - N is a flag for PAPI Native events;
     - CC defines one of three chips;
     - RRRRR defines one of 32 registers;
     - EE defines one of four events.

  The names of these event definitions are identical to those found in Cray documentation,
  except that they have a prepended 'X1_' on each name.
*/

#define _P_ 0x1000
#define _E_ 0x2000
#define _M_ 0x3000

#define X1_CHIP_DECODE(code)	(code & 0xf000)
#define X1_COUNTER_DECODE(code) ((code >> 4) & 0xff)
#define X1_EVENT_DECODE(code)	(code & 0xf)

#define X1_NATIVE(chip, event) (PAPI_NATIVE_MASK | _##chip | (chip##CNTR_IDX_##event << 4) | (##chip##EV_##event >> (##chip##CNTR_IDX_##event << 1)))

/* Defines for counter value retrival from the array of counters */

/*
 * Following are the various kinds of events that can be counted in the sv2
 * performance counters.
 */

#define X1_P_EV_CYCLES			X1_NATIVE(P_, CYCLES)

#define X1_P_EV_INST_GRAD		X1_NATIVE(P_, INST_GRAD)

#define X1_P_EV_INST_DISPATCH		X1_NATIVE(P_, INST_DISPATCH)
#define X1_P_EV_ITLB_MISS		X1_NATIVE(P_, ITLB_MISS)
#define X1_P_EV_STALL_PARB_E_FULL	X1_NATIVE(P_, STALL_PARB_E_FULL)
#define X1_P_EV_STALL_VU_FUG_REG	X1_NATIVE(P_, STALL_VU_FUG_REG)

#define X1_P_EV_INST_SYNCS		X1_NATIVE(P_, INST_SYNCS)
#define X1_P_EV_INST_GSYNCS		X1_NATIVE(P_, INST_GSYNCS)
#define X1_P_EV_STALL_IFU_ICACHE	X1_NATIVE(P_, STALL_IFU_ICACHE)
#define X1_P_EV_STALL_VU_REG		X1_NATIVE(P_, STALL_VU_REG)

#define X1_P_EV_INST_AMO		X1_NATIVE(P_, INST_AMO)
#define X1_P_EV_DCACHE_BYPASS_REF	X1_NATIVE(P_, DCACHE_BYPASS_REF)
#define X1_P_EV_STALL_IFU_BRANCH_PRED	X1_NATIVE(P_, STALL_IFU_BRANCH_PRED)
#define X1_P_EV_STALL_VU_OTHER_REG	X1_NATIVE(P_, STALL_VU_OTHER_REG)

#define X1_P_EV_INST_A			X1_NATIVE(P_, INST_A)
#define X1_P_EV_STALL_SYNC_CHECKIN	X1_NATIVE(P_, STALL_SYNC_CHECKIN)
#define X1_P_EV_STALL_IFU_DU_FULL	X1_NATIVE(P_, STALL_IFU_DU_FULL)
#define X1_P_EV_STALL_VU_CNTR5		X1_NATIVE(P_, STALL_VU_CNTR5)

#define X1_P_EV_INST_S_INT		X1_NATIVE(P_, INST_S_INT)
#define X1_P_EV_INST_MSYNCS		X1_NATIVE(P_, INST_MSYNCS)
#define X1_P_EV_STALL_DU_ACT_LIST_FULL	X1_NATIVE(P_, STALL_DU_ACT_LIST_FULL)
#define X1_P_EV_STALL_VU_NO_INST	X1_NATIVE(P_, STALL_VU_NO_INST)

#define X1_P_EV_INST_S_FP		X1_NATIVE(P_, INST_S_FP)
#define X1_P_EV_STLB_MISS		X1_NATIVE(P_, STLB_MISS)
#define X1_P_EV_STALL_DU_ASU_FULL	X1_NATIVE(P_, STALL_DU_ASU_FULL)
#define X1_P_EV_STALL_LSU_LSYNCVS	X1_NATIVE(P_, STALL_LSU_LSYNCVS)

#define X1_P_EV_INST_MISC		X1_NATIVE(P_, INST_MISC)
#define X1_P_EV_VTLB_MISS		X1_NATIVE(P_, VTLB_MISS)
#define X1_P_EV_STALL_DU_VDU_FULL	X1_NATIVE(P_, STALL_DU_VDU_FULL)
#define X1_P_EV_STALL_VLSU_NO_INST	X1_NATIVE(P_, STALL_VLSU_NO_INST)

#define X1_P_EV_INST_BRANCH		X1_NATIVE(P_, INST_BRANCH)
#define X1_P_EV_CNTR9_BLANK_1		X1_NATIVE(P_, CNTR9_BLANK_1)
#define X1_P_EV_STALL_LSU_SYNC		X1_NATIVE(P_, STALL_LSU_SYNC)
#define X1_P_EV_STALL_VLSU_LB		X1_NATIVE(P_, STALL_VLSU_LB)

#define X1_P_EV_INST_MEM		X1_NATIVE(P_, INST_MEM)
#define X1_P_EV_CNTR10_BLANK_1		X1_NATIVE(P_, CNTR10_BLANK_1)
#define X1_P_EV_STALL_LSU_FOQ_FULL	X1_NATIVE(P_, STALL_LSU_FOQ_FULL)
#define X1_P_EV_STALL_VLSU_SB		X1_NATIVE(P_, STALL_VLSU_SB)

#define X1_P_EV_TLB_MISS		X1_NATIVE(P_, TLB_MISS)
#define X1_P_EV_ICACHE_FETCHES		X1_NATIVE(P_, ICACHE_FETCHES)
#define X1_P_EV_STALL_LSU_ORB_FULL	X1_NATIVE(P_, STALL_LSU_ORB_FULL)
#define X1_P_EV_STALL_VLSU_RB		X1_NATIVE(P_, STALL_VLSU_RB)

#define X1_P_EV_DCACHE_MISS		X1_NATIVE(P_, DCACHE_MISS)
#define X1_P_EV_DCACHE_INVALIDATE_E	X1_NATIVE(P_, DCACHE_INVALIDATE_E)
#define X1_P_EV_STALL_DU_SHADOW		X1_NATIVE(P_, STALL_DU_SHADOW)
#define X1_P_EV_STALL_VLSU_VM		X1_NATIVE(P_, STALL_VLSU_VM)

#define X1_P_EV_BRANCH_MISPREDICT	X1_NATIVE(P_, BRANCH_MISPREDICT)
#define X1_P_EV_DCACHE_INVALIDATE_V	X1_NATIVE(P_, DCACHE_INVALIDATE_V)
#define X1_P_EV_STALL_DU_INST_HOLD	X1_NATIVE(P_, STALL_DU_INST_HOLD)
#define X1_P_EV_STALL_VLSU_SREF		X1_NATIVE(P_, STALL_VLSU_SREF)

#define X1_P_EV_STALL_VU_CNTR14		X1_NATIVE(P_, STALL_VU_CNTR14)
#define X1_P_EV_STALL_IFU		X1_NATIVE(P_, STALL_IFU)
#define X1_P_EV_STALL_DU_SRQ_FULL	X1_NATIVE(P_, STALL_DU_SRQ_FULL)
#define X1_P_EV_STALL_VLSU_INDEX	X1_NATIVE(P_, STALL_VLSU_INDEX)

#define X1_P_EV_STALL_VLSU		X1_NATIVE(P_, STALL_VLSU)
#define X1_P_EV_STALL_DU		X1_NATIVE(P_, STALL_DU)
#define X1_P_EV_STALL_DU_ALSQ_FULL	X1_NATIVE(P_, STALL_DU_ALSQ_FULL)
#define X1_P_EV_STALL_VDU_NO_INST_VU	X1_NATIVE(P_, STALL_VDU_NO_INST_VU)

#define X1_P_EV_INST_V			X1_NATIVE(P_, INST_V)
#define X1_P_EV_INST_V_INT		X1_NATIVE(P_, INST_V_INT)
#define X1_P_EV_INST_V_FP		X1_NATIVE(P_, INST_V_FP)
#define X1_P_EV_INST_V_MEM		X1_NATIVE(P_, INST_V_MEM)

#define X1_P_EV_VOPS_VL			X1_NATIVE(P_, VOPS_VL)
#define X1_P_EV_ICACHE_MISS		X1_NATIVE(P_, ICACHE_MISS)
#define X1_P_EV_VOPS_VL_32BIT		X1_NATIVE(P_, VOPS_VL_32BIT)
#define X1_P_EV_CNTR17_BLANK_3		X1_NATIVE(P_, CNTR17_BLANK_3)

#define X1_P_EV_VOPS_INT_ADD		X1_NATIVE(P_, VOPS_INT_ADD)
#define X1_P_EV_BHT_PRED		X1_NATIVE(P_, BHT_PRED)
#define X1_P_EV_STALL_DU_AXQ_FULL	X1_NATIVE(P_, STALL_DU_AXQ_FULL)
#define X1_P_EV_STALL_VU_VM_REG		X1_NATIVE(P_, STALL_VU_VM_REG)

#define X1_P_EV_VOPS_FP_ADD		X1_NATIVE(P_, VOPS_FP_ADD)
#define X1_P_EV_BHT_CORRECT		X1_NATIVE(P_, BHT_CORRECT)
#define X1_P_EV_STALL_DU_SXQ_FULL	X1_NATIVE(P_, STALL_DU_SXQ_FULL)
#define X1_P_EV_CNTR19_BLANK_3		X1_NATIVE(P_, CNTR19_BLANK_3)

#define X1_P_EV_VOPS_INT_LOG		X1_NATIVE(P_, VOPS_INT_LOG)
#define X1_P_EV_JTB_PRED		X1_NATIVE(P_, JTB_PRED)
#define X1_P_EV_STALL_DU_CMQ_FULL	X1_NATIVE(P_, STALL_DU_CMQ_FULL)
#define X1_P_EV_STALL_VU_TLB_REG	X1_NATIVE(P_, STALL_VU_TLB_REG)

#define X1_P_EV_VOPS_FP_DIV		X1_NATIVE(P_, VOPS_FP_DIV)
#define X1_P_EV_JTB_CORRECT		X1_NATIVE(P_, JTB_CORRECT)
#define X1_P_EV_STALL_ASU_SRQ_OP	X1_NATIVE(P_, STALL_ASU_SRQ_OP)
#define X1_P_EV_STALL_VU_STORE_REG	X1_NATIVE(P_, STALL_VU_STORE_REG)

#define X1_P_EV_VOPS_INT_SHIFT		X1_NATIVE(P_, VOPS_INT_SHIFT)
#define X1_P_EV_JRS_PRED		X1_NATIVE(P_, JRS_PRED)
#define X1_P_EV_STALL_ASU_ALSQ_OP	X1_NATIVE(P_, STALL_ASU_ALSQ_OP)
#define X1_P_EV_CNTR22_BLANK_3		X1_NATIVE(P_, CNTR22_BLANK_3)

#define X1_P_EV_VOPS_FP_MULT		X1_NATIVE(P_, VOPS_FP_MULT)
#define X1_P_EV_JRS_CORRECT		X1_NATIVE(P_, JRS_CORRECT)
#define X1_P_EV_STALL_ASU_AXQ1_OP	X1_NATIVE(P_, STALL_ASU_AXQ1_OP)
#define X1_P_EV_CNTR23_BLANK_3		X1_NATIVE(P_, CNTR23_BLANK_3)

#define X1_P_EV_VOPS_LOAD_INDEX		X1_NATIVE(P_, VOPS_LOAD_INDEX)
#define X1_P_EV_VOPS_INT_MISC		X1_NATIVE(P_, VOPS_INT_MISC)
#define X1_P_EV_INST_LSYNCVS		X1_NATIVE(P_, INST_LSYNCVS)
#define X1_P_EV_VOPS_VL_64BIT		X1_NATIVE(P_, VOPS_VL_64BIT)

#define X1_P_EV_VOPS_STORE_INDEX	X1_NATIVE(P_, VOPS_STORE_INDEX)
#define X1_P_EV_VOPS_FP_MISC		X1_NATIVE(P_, VOPS_FP_MISC)
#define X1_P_EV_INST_LSYNCSV		X1_NATIVE(P_, INST_LSYNCSV)
#define X1_P_EV_STALL_VDU_SCM_VU	X1_NATIVE(P_, STALL_VDU_SCM_VU)

#define X1_P_EV_VOPS_LOADS		X1_NATIVE(P_, VOPS_LOADS)
#define X1_P_EV_ICACHE_HITS		X1_NATIVE(P_, ICACHE_HITS)
#define X1_P_EV_STALL_ASU_AXQ2_OP	X1_NATIVE(P_, STALL_ASU_AXQ2_OP)
#define X1_P_EV_CNTR26_BLANK_3		X1_NATIVE(P_, CNTR26_BLANK_3)

#define X1_P_EV_VOPS_STORE		X1_NATIVE(P_, VOPS_STORE)
#define X1_P_EV_INST_MEM_ALLOC		X1_NATIVE(P_, INST_MEM_ALLOC)
#define X1_P_EV_STALL_ASU_SXQ1_OP	X1_NATIVE(P_, STALL_ASU_SXQ1_OP)
#define X1_P_EV_CNTR27_BLANK_3		X1_NATIVE(P_, CNTR27_BLANK_3)

#define X1_P_EV_VOPS_LOAD_STRIDE	X1_NATIVE(P_, VOPS_LOAD_STRIDE)
#define X1_P_EV_INST_SYSCALL		X1_NATIVE(P_, INST_SYSCALL)
#define X1_P_EV_CNTR28_BLANK_2		X1_NATIVE(P_, CNTR28_BLANK_2)
#define X1_P_EV_STALL_VDU_SOP_VU	X1_NATIVE(P_, STALL_VDU_SOP_VU)

#define X1_P_EV_VOPS_STORE_STRIDE	X1_NATIVE(P_, VOPS_STORE_STRIDE)
#define X1_P_EV_BRANCH_TAKEN		X1_NATIVE(P_, BRANCH_TAKEN)
#define X1_P_EV_STALL_ASU_CRQ_OP	X1_NATIVE(P_, STALL_ASU_CRQ_OP)
#define X1_P_EV_STALL_VDU_NO_INST_VLSU  X1_NATIVE(P_, STALL_VDU_NO_INST_VLSU)

#define X1_P_EV_VOPS_LOAD_ALLOC		X1_NATIVE(P_, VOPS_LOAD_ALLOC)
#define X1_P_EV_INST_LOAD		X1_NATIVE(P_, INST_LOAD)
#define X1_P_EV_STALL_ASU_SRQ_DEST	X1_NATIVE(P_, STALL_ASU_SRQ_DEST)
#define X1_P_EV_STALL_VDU_SCM_VLSU	X1_NATIVE(P_, STALL_VDU_SCM_VLSU)

#define X1_P_EV_VOPS_STORE_ALLOC	X1_NATIVE(P_, VOPS_STORE_ALLOC)
#define X1_P_EV_DCACHE_INVALIDATE	X1_NATIVE(P_, DCACHE_INVALIDATE)
#define X1_P_EV_STALL_ASU_ALSQ_DEST	X1_NATIVE(P_, STALL_ASU_ALSQ_DEST)
#define X1_P_EV_STALL_VDU_SOP_VLSU	X1_NATIVE(P_, STALL_VDU_SOP_VLSU)

/* Now the Echip counter and event defines */

#define X1_E_EV_REQUESTS		X1_NATIVE(E_, REQUESTS)
#define X1_E_EV_MSYNCS			X1_NATIVE(E_, MSYNCS)
#define X1_E_EV_M_OUT_BUSY		X1_NATIVE(E_, M_OUT_BUSY)
#define X1_E_EV_REPLAYED		X1_NATIVE(E_, REPLAYED)
#define X1_E_EV_ALLOC_REQUESTS		X1_NATIVE(E_, ALLOC_REQUESTS)
#define X1_E_EV_GSYNCS			X1_NATIVE(E_, GSYNCS)
#define X1_E_EV_M_OUT_BLOCK		X1_NATIVE(E_, M_OUT_BLOCK)
#define X1_E_EV_REPLAY_WFVD		X1_NATIVE(E_, REPLAY_WFVD)
#define X1_E_EV_MISSES			X1_NATIVE(E_, MISSES)
#define X1_E_EV_MSYNC_PARTICIPANTS	X1_NATIVE(E_, MSYNC_PARTICIPANTS)
#define X1_E_EV_REQ_IN_BUSY_0		X1_NATIVE(E_, REQ_IN_BUSY_0)
#define X1_E_EV_REPLAY_PENDING		X1_NATIVE(E_, REPLAY_PENDING)
#define X1_E_EV_EVICTIONS		X1_NATIVE(E_, EVICTIONS)
#define X1_E_EV_GSYNC_PARTICIPANTS	X1_NATIVE(E_, GSYNC_PARTICIPANTS)
#define X1_E_EV_DROPS			X1_NATIVE(E_, DROPS)
#define X1_E_EV_REPLAY_ALLOC		X1_NATIVE(E_, REPLAY_ALLOC)
#define X1_E_EV_NOTIFIES		X1_NATIVE(E_, NOTIFIES)
#define X1_E_EV_STALL_MSYNC		X1_NATIVE(E_, STALL_MSYNC)
#define X1_E_EV_REQ_IN_BUSY_1		X1_NATIVE(E_, REQ_IN_BUSY_1)
#define X1_E_EV_REPLAY_WAKEUPS		X1_NATIVE(E_, REPLAY_WAKEUPS)
#define X1_E_EV_WRITEBACKS		X1_NATIVE(E_, WRITEBACKS)
#define X1_E_EV_STALL_GSYNC		X1_NATIVE(E_, STALL_GSYNC)
#define X1_E_EV_REQ_IN_BUSY_2		X1_NATIVE(E_, REQ_IN_BUSY_2)
#define X1_E_EV_REPLAY_MATCHES		X1_NATIVE(E_, REPLAY_MATCHES)
#define X1_E_EV_FORWARDED		X1_NATIVE(E_, FORWARDED)
#define X1_E_EV_STALL_BANK_ARB		X1_NATIVE(E_, STALL_BANK_ARB)
#define X1_E_EV_FLUSHREQ		X1_NATIVE(E_, FLUSHREQ)
#define X1_E_EV_REPLAY_FLIPS		X1_NATIVE(E_, REPLAY_FLIPS)
#define X1_E_EV_FWDREADALL		X1_NATIVE(E_, FWDREADALL)
#define X1_E_EV_STALL_BANK_FULL		X1_NATIVE(E_, STALL_BANK_FULL)
#define X1_E_EV_REQ_IN_BUSY_3		X1_NATIVE(E_, REQ_IN_BUSY_3)
#define X1_E_EV_CNTR7_BLANK_3		X1_NATIVE(E_, CNTR7_BLANK_3)
#define X1_E_EV_FWDREADSHARED		X1_NATIVE(E_, FWDREADSHARED)
#define X1_E_EV_STALL_REPLAY_FULL	X1_NATIVE(E_, STALL_REPLAY_FULL)
#define X1_E_EV_VWD_IN_BUSY_0		X1_NATIVE(E_, VWD_IN_BUSY_0)
#define X1_E_EV_UPGRADES		X1_NATIVE(E_, UPGRADES)
#define X1_E_EV_FWDGET			X1_NATIVE(E_, FWDGET)
#define X1_E_EV_STALL_TB_FULL		X1_NATIVE(E_, STALL_TB_FULL)
#define X1_E_EV_VWD_IN_BUSY_1		X1_NATIVE(E_, VWD_IN_BUSY_1)
#define X1_E_EV_CNTR9_BLANK_3		X1_NATIVE(E_, CNTR9_BLANK_3)
#define X1_E_EV_UPDATE			X1_NATIVE(E_, UPDATE)
#define X1_E_EV_STALL_VWRITENA		X1_NATIVE(E_, STALL_VWRITENA)
#define X1_E_EV_VWD_IN_BUSY_2		X1_NATIVE(E_, VWD_IN_BUSY_2)
#define X1_E_EV_MISSES_0		X1_NATIVE(E_, MISSES_0)
#define X1_E_EV_NACKS			X1_NATIVE(E_, NACKS)
#define X1_E_EV_PROT_ENGINE_IDLE	X1_NATIVE(E_, PROT_ENGINE_IDLE)
#define X1_E_EV_VWD_IN_BUSY_3		X1_NATIVE(E_, VWD_IN_BUSY_3)
#define X1_E_EV_MISSES_1		X1_NATIVE(E_, MISSES_1)
#define X1_E_EV_UPDATE_NACK		X1_NATIVE(E_, UPDATE_NACK)
#define X1_E_EV_MISSES_2		X1_NATIVE(E_, MISSES_2)
#define X1_E_EV_P_OUT_BUSY_0		X1_NATIVE(E_, P_OUT_BUSY_0)
#define X1_E_EV_DCACHE_INVAL_PKTS	X1_NATIVE(E_, DCACHE_INVAL_PKTS)
#define X1_E_EV_INVAL			X1_NATIVE(E_, INVAL)
#define X1_E_EV_MISSES_3		X1_NATIVE(E_, MISSES_3)
#define X1_E_EV_P_OUT_BUSY_1		X1_NATIVE(E_, P_OUT_BUSY_1)
#define X1_E_EV_REQ_IN_BUSY		X1_NATIVE(E_, REQ_IN_BUSY)
#define X1_E_EV_LOCAL_INVAL		X1_NATIVE(E_, LOCAL_INVAL)
#define X1_E_EV_MARKED_REQS		X1_NATIVE(E_, MARKED_REQS)
#define X1_E_EV_P_OUT_BUSY_2		X1_NATIVE(E_, P_OUT_BUSY_2)
#define X1_E_EV_VWD_IN_BUSY		X1_NATIVE(E_, VWD_IN_BUSY)
#define X1_E_EV_DCACHE_INVAL_EVENTS	X1_NATIVE(E_, DCACHE_INVAL_EVENTS)
#define X1_E_EV_MARKED_CYCLES		X1_NATIVE(E_, MARKED_CYCLES)
#define X1_E_EV_P_OUT_BUSY_3		X1_NATIVE(E_, P_OUT_BUSY_3)
#define X1_E_EV_P_OUT_BUSY		X1_NATIVE(E_, P_OUT_BUSY)

/* Now the Mchip counter and event defines */

#define X1_M_EV_REQUESTS		X1_NATIVE(M_, REQUESTS)
#define X1_M_EV_STALL_REPLAY_FULL	X1_NATIVE(M_, STALL_REPLAY_FULL)
#define X1_M_EV_CNTR0_BLANK_2		X1_NATIVE(M_, CNTR0_BLANK_2)
#define X1_M_EV_LOCAL			X1_NATIVE(M_, LOCAL)
#define X1_M_EV_IN_REMOTE		X1_NATIVE(M_, IN_REMOTE)
#define X1_M_EV_STALL_TDB_FULL		X1_NATIVE(M_, STALL_TDB_FULL)
#define X1_M_EV_I_IN_BUSY		X1_NATIVE(M_, I_IN_BUSY)
#define X1_M_EV_FWDREADSHARED		X1_NATIVE(M_, FWDREADSHARED)
#define X1_M_EV_UPDATE			X1_NATIVE(M_, UPDATE)
#define X1_M_EV_STALL_MM_RESPQ		X1_NATIVE(M_, STALL_MM_RESPQ)
#define X1_M_EV_E_OUT_BUSY_0		X1_NATIVE(M_, E_OUT_BUSY_0)
#define X1_M_EV_OUT_REMOTE		X1_NATIVE(M_, OUT_REMOTE)
#define X1_M_EV_NONCACHED		X1_NATIVE(M_, NONCACHED)
#define X1_M_EV_STALL_ASSOC		X1_NATIVE(M_, STALL_ASSOC)
#define X1_M_EV_E_OUT_BUSY_1		X1_NATIVE(M_, E_OUT_BUSY_1)
#define X1_M_EV_CNTR3_BLANK_3		X1_NATIVE(M_, CNTR3_BLANK_3)
#define X1_M_EV_SHARED			X1_NATIVE(M_, SHARED)
#define X1_M_EV_STALL_VN1_BLOCKED	X1_NATIVE(M_, STALL_VN1_BLOCKED)
#define X1_M_EV_E_OUT_BUSY_2		X1_NATIVE(M_, E_OUT_BUSY_2)
#define X1_M_EV_CNTR4_BLANK_3		X1_NATIVE(M_, CNTR4_BLANK_3)
#define X1_M_EV_FORWARDED		X1_NATIVE(M_, FORWARDED)
#define X1_M_EV_PROT_ENGINE_IDLE	X1_NATIVE(M_, PROT_ENGINE_IDLE)
#define X1_M_EV_E_OUT_BUSY_3		X1_NATIVE(M_, E_OUT_BUSY_3)
#define X1_M_EV_FWDREAD			X1_NATIVE(M_, FWDREAD)
#define X1_M_EV_SUPPLYINV		X1_NATIVE(M_, SUPPLYINV)
#define X1_M_EV_NUM_REPLAY		X1_NATIVE(M_, NUM_REPLAY)
#define X1_M_EV_E_OUT_BLOCK_0		X1_NATIVE(M_, E_OUT_BLOCK_0)
#define X1_M_EV_INVAL_1			X1_NATIVE(M_, INVAL_1)
#define X1_M_EV_SUPPLYDIRTYINV		X1_NATIVE(M_, SUPPLYDIRTYINV)
#define X1_M_EV_STALL_REQ_ARB		X1_NATIVE(M_, STALL_REQ_ARB)
#define X1_M_EV_E_OUT_BLOCK_1		X1_NATIVE(M_, E_OUT_BLOCK_1)
#define X1_M_EV_INVAL_2			X1_NATIVE(M_, INVAL_2)
#define X1_M_EV_SUPPLYSH		X1_NATIVE(M_, SUPPLYSH)
#define X1_M_EV_STALL_MM		X1_NATIVE(M_, STALL_MM)
#define X1_M_EV_E_OUT_BLOCK_2		X1_NATIVE(M_, E_OUT_BLOCK_2)
#define X1_M_EV_E_OUT_BUSY		X1_NATIVE(M_, E_OUT_BUSY)
#define X1_M_EV_SUPPLYDIRTYSH		X1_NATIVE(M_, SUPPLYDIRTYSH)
#define X1_M_EV_SECTION_BUSY		X1_NATIVE(M_, SECTION_BUSY)
#define X1_M_EV_E_OUT_BLOCK_3		X1_NATIVE(M_, E_OUT_BLOCK_3)
#define X1_M_EV_E_OUT_BLOCK		X1_NATIVE(M_, E_OUT_BLOCK)
#define X1_M_EV_SUPPLYEXCL		X1_NATIVE(M_, SUPPLYEXCL)
#define X1_M_EV_AMO			X1_NATIVE(M_, AMO)
#define X1_M_EV_I_OUT_BUSY		X1_NATIVE(M_, I_OUT_BUSY)
#define X1_M_EV_INVAL_3			X1_NATIVE(M_, INVAL_3)
#define X1_M_EV_NACKS			X1_NATIVE(M_, NACKS)
#define X1_M_EV_AMO_HIT			X1_NATIVE(M_, AMO_HIT)
#define X1_M_EV_I_OUT_BLOCK		X1_NATIVE(M_, I_OUT_BLOCK)
#define X1_M_EV_INVAL_4			X1_NATIVE(M_, INVAL_4)
#define X1_M_EV_UPDATENACK		X1_NATIVE(M_, UPDATENACK)
#define X1_M_EV_CNTR12_BLANK_1		X1_NATIVE(M_, CNTR12_BLANK_1)
#define X1_M_EV_NTWK_OUT_BUSY_0		X1_NATIVE(M_, NTWK_OUT_BUSY_0)
#define X1_M_EV_FWDGET			X1_NATIVE(M_, FWDGET)
#define X1_M_EV_PEND_DROP		X1_NATIVE(M_, PEND_DROP)
#define X1_M_EV_CNTR13_BLANK_1		X1_NATIVE(M_, CNTR13_BLANK_1)
#define X1_M_EV_NTWK_OUT_BUSY_1		X1_NATIVE(M_, NTWK_OUT_BUSY_1)
#define X1_M_EV_FLUSHREQ		X1_NATIVE(M_, FLUSHREQ)
#define X1_M_EV_INVAL			X1_NATIVE(M_, INVAL)
#define X1_M_EV_CNTR14_BLANK_1		X1_NATIVE(M_, CNTR14_BLANK_1)
#define X1_M_EV_NTWK_OUT_BLOCK_0	X1_NATIVE(M_, NTWK_OUT_BLOCK_0)
#define X1_M_EV_CNTR14_BLANK_3		X1_NATIVE(M_, CNTR14_BLANK_3)
#define X1_M_EV_TB_LB_HIT		X1_NATIVE(M_, TB_LB_HIT)
#define X1_M_EV_CNTR15_BLANK_1		X1_NATIVE(M_, CNTR15_BLANK_1)
#define X1_M_EV_NTWK_OUT_BLOCK_1	X1_NATIVE(M_, NTWK_OUT_BLOCK_1)
#define X1_M_EV_CNTR15_BLANK_3		X1_NATIVE(M_, CNTR15_BLANK_3)
